1. Field of the Invention
The present invention relates to a method and apparatus of time-to-digital converter (TDC), in particular to a TDC that has a very high resolution.
2. Description of Related Art
Time-to-digital converter (TDC) is well known in prior art. FIG. 1 depicts a schematic diagram of a prior art TDC 100, which comprises: a delay chain comprising a plurality of serial delay cells 110_1, 110_2, 110_3, and so on; an array of data flip-flops comprising DFF 120_1, 120_2, 120_3, and so on; and a thermometer-code decoder 130. The delay chain receives an input clock CLK and generates a plurality of delayed signals D(1), D(2), D(3), and so on. All delay cells (110_1, 110_2, 110_3, and so on) have substantially the same circuits, and therefore cause substantially the same amount of delay to their respective inputs. Let the delay caused by each of said delay cells be d. The delayed signals (i.e. D(1), D(2), D(3), and so on) from said delay cells (i.e. 110_1, 110_2, 110_3, and so on) are provided as inputs to said array of data flip-flops (i.e. 120_1, 120_2, 120_3, and so on), resulting in a plurality of decisions (i.e. Q(1), Q(2), Q(3), and so on), respectively. For instance, D(1) from delay cell 110_1 is provided to DFF 120_1, resulting in decision Q(1). All data flip-flops (i.e. 120_1, 120_2, 120_3, and so on) are triggered by a reference clock REF; it is the timing difference between the input clock CLK and the reference clock REF that we want the TDC circuit 100 to detect and digitize. Thermometer-code decoder 130 receives said decisions (i.e. Q(1), Q(2), Q(3), and so on) from said data flip-flops (i.e. 120_1, 120_2, 120_3, and so on) and converts them into a digital output TE (which stands for “timing estimate”) representing a estimated timing difference between the input clock CLK and the reference clock REF.
FIG. 2 shows an exemplary timing diagram for a prior art TDC using 8 delay cells and 8 data flip-flops. In this example, the digital output TE is obtained by summing decisions from all data flip-flops, i.e. TE is equal to Q(1)+Q(2)+Q(3)+ . . . +Q(8). The estimated timing difference between the input clock CLK and the reference CLK in this diagram is thus TE·d=4d, where d is the amount of delay caused by each delay cell. Note that the output code group for TE in this embodiment is {0, 1, 2, . . . , 8}. In an alternative embodiment, an offset is introduced to the digital output TE so that output code group for TE is {−4, −3, −2, −1, 0, 1, 2, 3, 4}. The offset can be introduced by forcing TE=−4+Q(1)+Q(2)+Q(3)+ . . . +Q(8) and at the same time inserting four delay cells (not shown in the figure) between the reference clock CLK and the data flip flops. The offset is needed for a digital PLL (phase lock loop) application since in a steady state the timing difference (between an input clock and a reference clock) as reported by a TDC needs to be nearly zero. In an alternative embodiment using an odd number of delay cells and data flip-flops, the offset is introduced so that the code group for TE is {±1/2, ±3/2, ±5/2, . . . }. In this case, there is no “0” in the code group and ±1/2 is considered “virtually zero.” For a digital PLL application, again, in a steady state the timing difference (between an input clock and a reference clock) as reported by a TDC needs to nearly true zero or virtually zero.
The timing resolution for a prior art TDC is limited by an amount of delay caused by a delay cell. For example, in modern CMOS (complementary metal-oxide semiconductor) technology, a delay cell is usually embodied by a buffer circuit, which causes a delay of no less than 20 ps. The timing resolution for a prior art TDC built in a modern CMOS circuit is therefore limited to no finer than 20 ps.
What is needed is an apparatus and method to achieve a high timing resolution despite using a circuit that causes an amount of delay no less than 20 ps.